Pulse counting and checking apparatus



July 5, 1960 M. R. CANNON PULSE coummc AND CHECKING APPARATUS 3 Sheets-Sheet 1 Filed June 25, 1958 TITITTTIT? S R Y mm m n m w M93 E w o W n "U ml a A Ya 55m 0 a m 2%: R a AG! IWSR W w m M Y B uly 5, 1960 M. R. CANNON 2,944,189

PULSE COUNTING AND cmzcxmc APPARATUS Filed June 25, 1958 3 Sheets-Sheet 2 r 28 34 V 7 42 36 i A 5 \38 v 3 d I B 3 I 1 INVENTOR Max well A. Cannon ATTORNEYS y 1950 M. R. CANNON 2,944,189

PULSE COUNTING AND CHECKING APPARATUS Filed June 25, 1958 5 Sheets-Sheet 5 BRQFH I 27 COUNTER u} 26 LI"U LI"LI"U-LJ U"LJ LJ' mus L 27 o COUNTER L 26 CLOCK U LJ LJ U LJTLHJ L.I U

BRUSH l u] g 27 27d 5H cow/r51? U\ W BRUSH aou/vrse U 9 finnnr-LmI-Lnnr' 28 if 22 Z3 Z4 Z3- Z6 7 58 t3 INVENTOR Maxwell R. Carma ATTORNEY8 tinned States PULSE CGUNTING AND CIECKING APPARATUS Maxwell R. Cannon, Endicott, N.Y., assignor to International Business Machines Corporation, New York, N.Y., a corporation of New York Filed June 25, 1958, Ser. No. 744,35d

'15 Claims. (Cl. 315-846) have not heretofore been regarded as satisfactory in situations where an extremely rapid, and in many cases nondestructive, read-out of the stored pulse count is needed. One such application is the checking or verification of data recorded in tabulating cards or the like. One may wish, for example, to verify serial numbers in cards which supposedly are arranged in a progressively ascending order. A progressive count against which the card numbers are to be verified is maintained in a counter, with the stored count being read out nnde structively and increased by l for each card verified. There is an increasing demand for verifiers having counters which can store and read out their reference numbers at a rate much higher than that of the conventional electromechanical counters now available. Prior gas tube counters have not been regarded with favor for this purpose because their read-out periods have not been sufficiently brief to warrant their substitutionfor electromechanical counters. Moreover, gas tube counters heretofore have not lent themselves to nondestructive read-out, except by the roll-out method which not atent G only is slow but entails some risk of destroying the stored data as well. 7

There are several modes of'verifioation, such as serial number verification, mentioned above, gang verification in which the identifying numbers of all cards in a run are checked against a stored master number that is read out nondestructively and without change, and ran dom verification in which the stored number is read out destructively and is replaced by an unrelated number each time. Present-day conditions point toward the need for verifiers which can handle up to 10,000 cards per .minute for serial or gang verification and around 4,000

cards per minute for random verification. Verifiers of prior design cannot even approach these speeds, but

by using the principles of the present invention one may easily attain these high output rates.-

An object of the present invention is to provide a practical gas tube counter circuit having novel read-out features which enable the stored count to be read out at the rate required in high speed operations of the magnitude indicated hereinabove.

Another object is to provide a gas tube counter circuit in which this high read-out rate may be attained without any risk of destroying the stored data, for those applications where a nondestructive read-out is re quired.

Still another object is ot provide "a high speed veri- 2 fication apparatus which is completely fail-safe in its openations.

A further object is to provide gas tube counter circuit which is adapted to operate with transiston'zed driving and output stages.

A still further object is to provide a fail-safe verification circuit using solid-state elements for performing all of the required error checks such as the detection of incorrect marking, double marking and failure to mark.

These and other objects will become apparent from the following detailed description of the accompanying drawings.

In the drawings:

Fig. 1 is a diagram of a counter circuit employing a gas tube counter having a nondestructive read-out constructed in accordance with this invention;

Fig. 2 is a view showing various wave forms applicable at various points in the drive circuit for the gas tube counter of Fig. 1;

Fig. 3 is a view showing a circuit diagram of the Vcrification circuit of the present invention;

Fig.4 is a view illustrating signal wave forms fed to the circuit of this invention when a particular card being verified is found to be correctly marked;

Fig. 5 is similar to Fig. 4 only showing a signal resulting from erroneous marking of a tabulating card;

Fig. 6 is similar to Fig. 4 only showing signal resulting from the double marking of'a tabulating card;

Big. 7 is similar to Fig. 4- only showing the signal re sulting from a failure to mark a particular card;

Fig. 8 is a circuit diagram of a fail-safe tn'gger used in the verification circuit of this invention.

Turning to Figs. 1 and 2, which illustrate a singleorder counter embodying the invention, the multicathode gas tube 10 has its anode .11 connected to a B{ source of about 400 volts. The resistor 12 may have a valve of about 470K. The cathodes of the tube 10 are numbered 0 to 9, inclusive, and each is connected in parallel to the anode electrodes of two diodes, d and dug, d and a etc. Each even diode (dug, d etc.) is commonly connected by line 13 and timing bus 14- to resistor 15. Resistor 15 is connected between -20 volts and the base of inverter transistor T an NPN type. Each odd diode (d d etc.) is connected to succeeding outputs of a ring counter 17. 'The ring counter samples or strobes each cathode in turn by providing pulses to the various cathodes 0 to 9 successively at times respectively corresponding to the digits from 0 to 9 in the basic timing cycle of the verifying machine or other device which the counter is being employed. The ring is advanced by a suitable clock pulse generator 60 which furnishes clock pulses at a standard repetition rate as determined by the basic machine cycle or other timing period. Any other equivalent sampling or strobing means may be provided in lieu of the clock 60 and timing ring 17.

The tube 10 is adapted to count pulses furnished by a suitable source to represent any of the digits from If the numerical count stored inthe tube 10 is 5, for example, a dischargeis maintained between plate 11 and cathode 5. Under these conditions the diode d is forwardly biased, and current flows through (1' there is obtained a negative pulse output across resistor- 16 at digit time 5.

The driving circuit for the gas tube is illustrated as comprising two transistors T and T and associated circuitry. Other equivalent means employing vacuum tubes may be substituted; however, it is one of the objectives of the'present invention to provide a counter which will use transistorized driving and output stages. To the input condenser 18 are fed pulses in a number which is a function of the correct value of the information supposedly recorded on the card or other record that is being verified. This can be donein any conventional way.

Assuming that the disclosed counter is to be employed for storing serial numbers, the initial entry into the counter may be obtained by scanning a master card containing the first number of the series. By conventional means (not shown) the digital value in each order or column 'of the scanner number is converted to a corresponding series of positive pulses which are fed through the input condenser 18 to transistor T Thereafter, for each card verified, a single positive pulse only is applied to transistor T It is understood, of course, that this will occur in the units order of a multiorder counter, with carryover between orders when necessary. The carryover means and the additional orders of the counter are not illustrated herein because they are not essential to an understanding of the invention'and may readily be provided by a person skilled in the art.

Each positive pulse applied through condenser 18 to transistor T decreases the collector current in T to lower the voltage at point 20 from +20 volts to 60 volts as determined by the action of the clamping diode 21. When condenser 18 has charged, the transistor T returns to its normal state and point 20 again returns to +20 volts. This provides an output pulse 22, Fig. 2, to the guide G of the gas tube 10, Fig. 1. Point 23 meanwhile has made the same kind of excursion as point 20 but due to the fact that transistor T is a PNP type, the positive excursion of this point provides an output at point 24 as shown by, pulse 25, Fig. 2, for guide G It is necessary, for reasons explained below, that these two pulses 22 and 25 fed to the guides G and G of counter tube 10 be displaced somewhat in time with respect to each other.

Before counting begins, the discharge in tube 10 is between plate 11 and cathode 0. Thenegative pulse 22 causes the discharge to'transfer to guide G The negative pulse 25 transfers the discharge to guide G and after the expiration to pulse 25 the discharge shifts to cathode 1. Further input pulses to the driving circuit will step the discharge along from cathode to cathode.

'When the dischargeis located at a particular cathode,

the voltage of that cathode rises to forward-bias its evennumbered diode. Its odd-numbered diode remains blocked until unblocked by the ring counter 17 as previously described. The output pulse from the counter, taken across resistor 16 in a time interval representative of the count stored in the; tube 10, is fed to the verification circuit which is illustrated in Fig. 3. A verification circuit of this kind is provided for each column of the numbers being verified.

Suitable reset means (not shown) is provided for resetting the counter 10 to its fzero condition. ,1 Reset of the counter tube merely involves opening the cathode I circuits of the cathodes 1 to 9 and biasing cathode 0 sufliciently negative to establish the glow discharge them. During gang or serial verification the counter 10 is reset only at the end of a card run. During random. verification reset occurs after each read-out, which would be a destructive read-out in each instance.

7 Referring to Fig. 3, pulse 26 represents the'counter output obtained fromtransistor T of Fig. 1. Pulse 27 'is fed to the verification circuit from the reading brushes or scanning means .which scan the tabulating card being ;verifi ed. Pulses 28 are clock pulses from clock pulse generator 60 which is synchronized with the scanning at digit position 5 in the particular column thereof being scanned. Assuming that the reference number stored in counter 10 is 5 for this particular card column, the gas tube counter circuit will provide a read-out pulse 26 to the verification circuit of Fig. 3 at time t A The clock generator 60 (Fig. 1) provides pulses 28 at each of the digit time intervals, including time 1 It will now be shown that under the conditions of Fig. 4, that is with an assumed correct marking of the tabulating card, no error signal will result.

Referring to Fig. 3, an inverter 29 provides a positive pulse output to the negative AND circuit or gate 30 in response to the negative reading brush pulse 27 at time t effectively blocking this gate at time 1 Consequent- 1y, there is no pulse output to the OR circuit 31 on line 32. The reading brush pulse 27 is also fed along line 33 to the negative AND gate 34. The counter pulse 26 is 'fed to an inverter 35 along a line 36 to provide a positive pulse output on line 37 leading to the negative AND gate 34. Therefore, gate 34 is efiectively blocked at time t and no pulse output is fed to the OR gate 31 along line 38.

Reviewing the above, it is seen that at time t under assumed conditions of correct marking, the input voltage on leg A 'of negative AND gate 30 is up, while the input voltages on legs B and C are down, thus blocking the negative AND gate 30. With regard to negative 'AND gate 34, leg A is down and leg B is up, thus blocking this gate also. Consequently, no signal travels through either branch of the logical circuit to the stop trigger 43. Stop trigger 43 provides an indication of an error in the tabulating card being scanned whenever an output is obtained from the OR gate 31 and may op erate means to disable the card feeding mechanism, or 'it may reject the erroneously punched card or perform some similar function. As long as this trigger 43-does not receive a pulse from the logical circuit, the scanning operation and verification of tabulating cards continues in normal fashion.

marking of the tabulating card, it being assumed for Fig. 5 illustrates asequence of events due. to erroneous illustration that the card has a marking thereon at digit position 4 rather than at the correct digit position5. Referring to Fig. 3, at time 12, the voltage on leg-A of negative AND gate 34 is down, as is that of leg 13 also. It should be noted "that the output potential of'each of the inverters 29 and 35 is normally down and only goes 'up when a negative input is applied to said inverter. Consequently, at time negative AND gate 34 provides an output along line 38-to negative OR gate 31. Nega-' tive OR gate 31 provides an error signal through an emit-l ter follower 40, a line 41 (of which there is one for each ordei or column of the numbers being verified),

and a negative OR gate 42 tothe stop trigger 43. This trigger 43 provides an indication of the erroneous markf ing of the tabulating card being scanned in a manner to be explained later in connection with Fig. 8. V

Fig. 6 illu strates a typical problem of double marking,

that is a correct marking on the card column being scanned at digit position 5 coupled with an erroneous marking thereon at digit position 7. Referring again to Fig. 3, it can be seen that at time t no error signal is-fed to the stop trigger 43. However, at time 1 nega-' tive AND gate 34 provides an error signal in a manner similar to that .explained withreference to Fig. 5.

Fig. 7 illustrates what happens when there is a blank column on the card where there should be a column marked at position therein. At time t under these conditions, the voltages on all of the legs, A, B and C, of the negative AND gate 30, Fig. 3, are down, thus providing an error signal to the stop trigger 43.

Fig. 8 shows the fail-safe construction of the stop trigger 43. This trigger includes two transistors of opposite conductivity types, namely, T a PNP type, and T an NPN type. The trigger operates in a fashion such that if one transistor is conducting it will cause the other to conduct, and if one transistor is shut off if will cause the other to shut off. Let it be assumed that both transistors are reversely biased and consequently nonconducting. The application of a negative reset pulse 44 on line 51 through resistor 52 to the base of T will cause T to conduct. This will energize relay 46 by providing a current path from the ---20 volt supply through the relay and T Approximately -20 volts will appear at the collector of T The voltage divider action between 20 volts and +10 volts through the voltage divider consisting of the resistors 47, 48 and 49 will apply a forward bias on transistor T Now both transistors are conducting. Should an error signal be supplied from the output of negative OR gate 42 through condenser 50 to the base of T T .then will become nonconducting. The voltage drop across resistor 45 then is such as to reversely bias the transistor T also. The relay 46, having no closed current path through its winding, will become deenergized, and the circuitry controlled by relay 46 (not shown) will act accordingly. The card error signal may be manifested by shutting down the card feed, ejecting the defective card, etc. The diode 53 shunts any voltage developed inductively by the coil of the relay 46.

It can be seen that the trigger 43, if it fails, will fail in a safe manner. If the relay 46 or either or both of the transistors T and T should fail, the trigger 43 will operate the relay-controlled circuit to indicate an error. The same result is obtained by failure of these components of the trigger as would be obtained by the introduction of an error signal from OR gate 42. The same fail-safe result is also obtained if the gas tube counter circuit of Fig. 1 fails to provide a pulse output 26 during the strobing of its cathodes. This may be due to failure of any of the components of this counter circuit to function properly, even failure of the strobing means itself, namely, the ring counter 17. *If the input to the verification circuit consists of the brush pulse 27 alone, it \Till provide an output from negative AND gate 34 to drive trigger 43 to its nonconducting state.

What has been described is a specific embodiment of the present invention. Other embodiments obvious from the teachings herein to those skilled in the art are contemplated to be Within the spirit and scope of the following claims.

What is claimed is:

1. A gas tube pulse counter circuit including a multicathode gas discharge tube, means to advance a plate-tocathode discharge in said tube from one cathode to another as a function of a pulse input to said circuit, and a read-out means to read out nondestructively from said tube a count stored therein, said read-out means comprising a source of potential, pairs of first and second unidirectional current conducting devices, the devices of each pair being connected at one end thereof to a respective one of said tube cathodes, means connecting all of said first devices of said pairs of devices to said source of potential whereby a discharge between a selected cathode and the plate of said tube will forwardly bias the first device of the pair of devices associated with that cathode, means to advance a forward-biasing voltage from the second device of a pair to the second device of the next succeeding pair, and means to provide a read-out voltage upon the simultaneous forward biasing of both of the devices associated with the selected cathode.

2. A circuit as defined by claim 1 wherein the first and second unidirectional current conducting devices of each pair are diodes.

3. A circuit as defined by claim 2 wherein said connect-ing means includes an impedance, and said read-out voltage is developed across said impedance.

4. A circuit as defined by claim 2 wherein said means to advance a forward-biasing voltage includes a sequential conditioning means providing sequential pulse outputs from the various stages thereof, and means connecting each of said second devices to a separate stage of said counter.

S. A circuit as defined by claim 2 wherein the plate electrode of each diode is connected toits associated cathode of said gas discharge tube.

6. A circuit as defined by claim 3 wherein the cathode electrode of each first device is connected to said impedance and the plate electrode thereof is connected to its associated cathode of said gas tube, and the cathode electrode of each second device is connected to a separate stage of said conditioning means and said plate electrode thereof is connected to its associated cathode of said gas tube.

7. A gas tube pulse counter circuit including a multicathode gas discharge tube, means to advance a plate-t0- cathode discharge in said tube from one cathode to another as a function of a pulse input to said circuit, and a read-out means to read out nondestructively from said tube a count stored therein, said read-out means comprising a source of potential, means connecting all of said cathodes together, an impedance connecting said cathode connecting means to said potential source, normally nonconducting individual devices respectively associated with said cathodes, each device capable of being conditioned to provide a shunt path for the current of its cathode in the event said cathode is carrying said discharge, means for sequentially conditioning said nonconducting devices so that they become conductive in a timed sequence whereby the normally nonconducting device connected to said discharge-carrying cathode becomes conductive to decrease the cathode current flowing through said impedacne at a time which is representative of the count being read out, and means to detect said current decrease as a read-out indication of said count stored in said tube.

8. A circuit as defined by claim 7 wherein said cathode connecting means and said normally nonconducting devices are electrically isolated from each other.

9. A circuit as defined in claim 7 wherein said connecting means includes a common conductor, a unidirectional current conducting device associated with each of said tube cathodes, and means to connect said devices to said common conductor.

10. A circuit as defined by claim 7 wherein each of said normally non-conducting individual devices comprises a unidirectional current conducting device and wherein said sequential conditioning means comprises a ring counter and means to connect each of said normally non-conducting unidirectional current conducting devices to a separate stage of said counter.

11. A circuit as defined by claim 10 further including at least two cascaded transistorized inverters, means to feed the voltage developed across said impedance to the first of said inverters, and means to obtain an output from the last of said inverters as a read-out voltage indicative of the count in said tube.

12. A verification circuit for indicating the lack of positional comparison between an actual marking on a record and a correct marking thereof comprising a twoinput AND gate, a three-input AND gate, a two-input OR gate, means to feed a time positional pulse indicative of said actual marking on said record to one input of said two-input AND gate, means to feed an inverted time positional pulse indicative of said correct marking of'said record to the other input of said two-input AND gate, means to feed a time positional pulse indicative of said correct marking to one input of said three-input AND gate, means to feed an inverted time positional pulse indicativeof the actual marking on said record to another input of said three-input AND gate, means to feed a train of timing pulses to the last of said inputs to said three-input AND gate, means to feed the respective outputs of said AND gates to separate inputs of said OR gate, and means to indicate a pulse output from said OR gate as an indication of said lack of comparison between said actual marking on said record and said correct marking thereof.

13. A circuit as defined by claim 12 further including a bistable trigger, said trigger normally being in one stable state, means to feed the pulse output of said OR gate to said trigger to flip said trigger to the other of its stable states, and means to indicate a change in the state of said trigger as an indication of said lack of positional comparison.

14. A circuit as defined by claim 13 wherein said bistable trigger includes two transistors of opposite conductivity types, both of said transistors being conductive in one of said stable states and non-conductive in the other of said stable states.

15. A circuit as defined by claim 12 wherein said means to feed a time positional pulse indicative of the correct record marking comprises a gas tube 1 pulse counter circuit including a multi-cathode gas discharge tube, means to advance a plate to cathode discharge in said tube from one cathode to another as a function of a pulse input to said circuit, and a read-out means to read out non-destructively from said tube a count stored therein, said read-out means comprising a source of potential, pairs of first and second unidirectional current conducting devices, the devices of each pairbeing connected at one end thereof to a respective one of said tube cathodes, means connecting all of said first devices of said pairs of devices to said source of potential, wherebya discharge between a selected cathode and the plate of said tube will forwardly bias the first device of the pair of devices associated with that cathode, means to advance a forward-biasing voltage fromthe second device of a pair of the second device of the next succeeding pair and means to provide a read-out voltage upon the simultaneously forward biasing of both of the devices associated with the selected cathode.

References Cited in the file of this patent UNITED STATES PATENTS 2,851,220 Kimes Sept. 9,1958 2,851,534 Bray Sept, 9, 1958 2,859,339 Brady Nov. 4, 1958 l l t 1 i 

